Does downsizing of transistors increase chips performance ?

Written by
Nicolas Paugam

Does downsizing of transistors increase chips performance ?

Written by
Nicolas Paugam

Does downsizing of transistors increase chips performance ?

Written by
Nicolas Paugam

Does the downsizing of transistors  increase chips performance ?


Today the Bitcoin is mined with specific electronic devices dedicated only for this task, called ASIC. This has not always been the case, at the beginning, the Bitcoin was mined by classic processors. To have better performances and to have more chances in finding a block, ASICs have become inescapable, whereas processors (CPU), graphic processor units (GPU) and even ASICs which are not of the last generation are unusable because they cost more in electricity than they earn with the mining. The best ASIC miner uses a 7nm technology, and probably a new one coming soon uses  a 5nm technology. The question we would like to respond is, does the downsizing of transistors increase chips performance ? Performance in our case is relative to the mining and means efficient in energy.

To better understand this problem in detail, we are going to study electronics and see the origins of energetic wastes into electronic circuits. Secondly, thanks to a study we are going to see the difference in terms of power consumption between the 14nm and 7nm technology. In the second part we are going to see the history of the miner performances and finish by studying a concrete case on the ASIC miners from Bitmain to compare their performances with the different size transistor technologies.

Electronic part

Before going into the heart of the topic, I am going to talk about the functioning of a transistor and a simple logic gate. We will use the logic ‘0’ an ‘1’ like the minimal and maximal voltage called VSS and VDD in the analog world.

‘0’ ⇔ minimal voltage ⇔ VSS

‘1’ ⇔ maximal voltage ⇔ VDD

In CMOS technology there are two types of transistors, a N type and a P type figure 1. In digital electronics they have the same behavior as a switch. There are two possibilities: the current can  throw the transistor or it can not throw the transistor. The N type transistor has its source (S) connected to the minimum voltage. This transistor is switched on when a ‘1’ is applied on the gate (G) and switched off when a ‘0’ is applied on the gate. The P type is the complementary transistor, it is switched on when a ‘0’ is applied on its gate and switched off when a ‘1’ is applied.     

Figure 1 : a) Transistor type N  NMOS  b) Transistor type P PMOS    

To be more clear, take the example of the simplest logic gate figure 2, the inverter. It is composed of one N and P transistor. When the input in A is equal to ‘1’ the P transistor is off and the N one is on, Q is connected to vss and  also equal to ‘0’. When the input state is switched and becomes equal to ‘0’, the N transistor is off whereas the P one is on, which implies the output is equal to ‘1’. In this model, when one transistor is on, the other one is always off, no current can be thrown and there is no energetic waste. This model is not complex enough to understand and take into account the energetic  consumption.   

Figure 2 :Inverter made with a NMOS and PMOS

Obviously, the reality of physics is more complex. CMOS transistors have the behavior of a current source controlled by its gate. This current is dependent of the gate voltage and the threshold voltage. The threshold voltage is the minimum voltage to apply at the gate that the transistor starts to generate a current, the increase of the voltage at the gate involves the increase of the current generated by the transistor. It is also important to take into account capacitances of the circuit. To illustrate these words, we take an example of  two inverters, one connected by the other one  figure 3 . When the input A switches from the state ‘1’ to ‘0’ for example, the output climbs progressively from ‘0’ to ‘1’ the time to load parasitic capacitances. During this time the two transistors are closed at the same time and a current throws them. This is the first source of dynamic power consumption. To reduce it, it is possible to reduce the alimentation voltage or increase the threshold voltage. When capacitances are loaded, they have a potential energy equal to  12CU2, they lose this energy during the unload. This is the second dynamic power consumption, with C the total of parasitic capacitances and U the alimentation voltage. To minimize this dynamic power dissipation, it is necessary to reduce the capacitance in reducing the transistor size (in keeping the same technology) or reduce the alimentation voltage.

Figure 3 Inverter logic gate to another inverter Cdiff is the capacitance in the output transistors Cint, is the parasite capacitance generated by the conexion Cgate is the capacitance cause by the gate of input transistors

In an electronic circuit there are also static power consumptions, which are caused by leakage currents. A transistor in off mode, when the gate voltage is below the threshold voltage is not totally locked, there is always a small current throwing the transistor. This current is higher when the voltage threshold decreases, the rising of temperature also increase this current. Another effect with the transistor downsizing is reduction of the insulator at the gate level, which implies that this insulator lets pass some electrons by tunnel effect. The diminution of the alimentation voltage can reduce this leakage current. [1]

To make a brief summary of issues can appear when we would like to decrease the transistor size.

In decreasing the transistor, the area decreases, which implies the diminution of parasitic capacitance, however to keep  good performances, the insulator at the gate level is  reduced which implies the increasing of capacitance per area and also implies the rising of static leakage current. It’s also possible to reduce the alimentation voltage, but to keep the same performances, the threshold voltage needs to be reduced and involves an increase in power consumption. When we want to continually decrease the size of transistors that we earn in consumption by a way, we lose it by another way to keep a  good performance. 

To go further, here is a video on Youtube demonstrating how to design an inverter.

To be more specific an article written by “ The university of southern California” [2] shows the difference of power consumption  between different size technologies and alimentation voltage. Twelve simulations have been made with different reference circuits, on the figure 4 shows the stimulation of the power consumption for the “c432 benchmark” circuit. 

From a point of view of the power consumption, the FF (FinFet) 7 nm technology is not better than the CMOS 14nm supplied in 0.55V.  To be better, the FF 7nm needs to have an alimentation voltage in 0.3V and have a threshold voltage equal to 0.32V ! As a reminder, the transistor should be off when the voltage on the gate is below at the threshold voltage.

Figure 4 : Comparisons of consumption according to the different technologies used for the circuit “c432 benchmark”. 

The downsizing of transistors from the 70s had always matched with the increase of the performance in speed and power consumption. Since the size of the transistors have reached tens of nanometers, it is more and more complicated to do better in the power consumption and the speed at the same time.  

The Bitcoin and its miners

So, let's talk about bitcoin miners now! 

To mine bitcoins the goal is to have the hash rate of the SHA256 algorithm the higher possible in order to have more chances to earn the 6.25 bitcoins reward (currently). It’s also important to have as little as possible power consumption for mining. The electricity is the major cost of the mining and only the efficient miners are profitable. You can see the evolution of the hash rate versus price of bitcoin if function of the time and miner periods on the figure 5.

At the beginning, bitcoins could be mined using a classic processor. Then GPUs arrived and offered better efficiency and  hash rate. GPUs are composed of hundreds of small and efficient CPUs.

When FPGAs appeared, their energy efficiency was multiplied by ten. FPGAs are totally different than processors, they are devices that are based around a matrix of configurable logic blocks. They can do several operations at the same time whereas CPUs can only make one operation at the same time. They are programmable and it is possible to implement the function desired whereas CPUs are versatile and must contain many instruction sets that makes them inefficient.

First ASICs made to mine bitcoins gained a lot of efficiency compared to the FPGA. More complex and more expensive than FPGA, ASICs are far better in terms of energy efficiency and hash rate (the first one had a hash rate 200 times better than GPU). Today the best ASIC miner has a hash rate 50,000 times superior and an energetic efficiency 10,000 times better than the best GPU used to mine bitcoin (S19 pro vs 5870x6) [4].

Figure 5 : evolution of the hash rate versus price of bitcoin if function of the time and miner periods. IEA, Bitcoin price and hashrate, 2010-2018, IEA, Paris
Figure 6 : IEA, Efficiency of bitcoin mining hardware, IEA, Paris

ASICs can be so efficient to “calculate” the SHA256 hash algorithm, because this algorithm needs only logical functions and additions. Logical functions are extremely simplistic and it’s very easy to ameliorate their efficiency ; additions also are simplistic and only require combinational logic. It’s also possible to design this electronics at the transistor level and gain even more efficiency. To make the comparison of efficiency with CPU, the most efficient ASIC has a hash rate 100,000,000 times better and energetic efficiency 1,000,000 times better than the less efficient CPU mining bitcoins figure 6.

Study of the Bitmain chips

The chip of the first generation for bitcoin mining is the BM1380 ; it was made in 55nm [5]. The chips BM1382, BM1384 and BM1385 were designed in 28nm and are respectively the 2nd, the 3rd and the 4th chips generation. An impeccable job was done to increase efficiency of 28nm chips. Since the BM1382, where they used the logic gates provided by the manufacturer, to the BM1385 where they designed, at the transistor level, their own logic gates, efficiencies were multiplied by three. The table 1 shows the characteristics of Bitmain chips in function of their alimentation voltage. As showcased in Figure 7, we can see that by decreasing the alimentation voltage, the energetic efficiency increase, and that by increasing the alimentation voltage, the hash rate is rising. 

Table 1 :

the characteristics of Bitmain chips in function of their alimentation voltage

Figure 7 : Evolution of the energy performance according to the chips and their supply voltage.  

The following chips are directly integrated into the “S” type of miner; Data seen on Table 2 come from the “ASIC miner value” web site [6].

Figure 8 : Evolution of the energy performance according to the evolution of the chip and Bitmain miner.

From the first chip made, there is a perpetual and linear increase of the miner chips performance (figure 8). There is not a real gap when there is a new technology. By doing the design at the transistor level there is a continuous improvement of the chip (even for the same technology). It’s also important to take into account the improvement of the PCB board. Chips used in S17 and in  S17pro are the same, likewise for chips used in S19 and S19pro. On “Zeus Mining” [7] website we can find a guide which explains the behavior of the electronics of the miner. Concerning the S19 and the S19pro, the alimentation  voltage of the chips is down from 0.36V to 0.32V. That implies two things, there is an increase of 13.6% of the energy efficiency and a decrease of 19.7% of the hash rate. The S19 has three hash boards, each board contains 76 chips, there are 228 chips in the S19. To keep the same power consumption, the S19pro has three hash boards, each board contains 114 chips,  there are 228 chips in the S19pro  figure 9.

Figure 9 : a) hash board of S19 b) hash board of S19pro


To have a global vision of the electronic, in answering the following question does the downsizing of transistors increase the chip performance (every time)? In the general case the answer is absolutely not. With the downsizing of the transistor there is an increase of leakage current, not every electronics application needs performance. In regard to bitcoin mining, the size reduction of transistors allows an increase of the efficiency but comes more and more marginal. A better conception of the architecture plays a major role in the increase of efficiency, moreover the electronics design and especially the layout conception is so much harder when transistors become smaller. It’s not enough to reduce the size of the transistor to  assure that electronics have the best efficiency.

Further discussion 

We would like to discuss the sovereignty of ASIC miner and more generally about  the localization of the ASIC foundry. Very few companies made ASIC miner for bitcoins, their designs and their fabrications are located in small areas. This monopolization is totally the reverse of the Bitcoin spirit. Today if you want to fabricate an ASIC there are few choices concerning the foundry and the country. The figure 10 shows different companies and countries doing subcontracting for the realization of ASIC (the area is proportional to the revenue). Intel for example is not represented because they produce their processor into their own foundry.

Figure 10 : ASIC manufacturers. From CNBC/TrendForce: Semiconductor Sales

Figure 11 : Semiconductor manufacturers. From Mordor Inteligence: Semiconductor Foundry Market


 [1] CHAUHAN, Yogesh Singh, LU, Darsen, VENUGOPALAN, Sriramkumar, et al. FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press, 2015.

[2] XIE, Qing, LIN, Xue, WANG, Yanzhi, et al. Performance comparisons between 7-nm FinFET and conventional bulk CMOS standard cell libraries. IEEE Transactions on Circuits and Systems II: Express Briefs, 2015, vol. 62, no 8, p. 761-765.